Ultra Ethernet Verification IP
Truechip's Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC. Truechip's UE VIP is compliant with IEEE standard 802.3-2018 & UE Specifications V1.0. This VIP is light weight with easy plug-and-play interface so that there is no hit on the design cycle time.
Key Benefits
	- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
 
	- Unique development methodology to ensure the highest levels of quality
 
	- Availability of Compliance & Regression Test Suites
 
	- 24X5 customer support
 
	- Unique and customizable licensing models
 
	- Exhaustive set of assertions and coverage points with connectivity example for all the components
 
	- Consistency of interface, installation, operation, and documentation across all our VIPs
 
	- Provide complete solution and easy integration in IP and SoC environment
 
Features
	- Supports AI base profile.
 
	- UET features: Message semantics, Packet delivery, tx congestion control sublayers
 
	- PDS layer supports RUD, ROD and UUD PDS ordering modes.
 
	- PDS supports single and multiple PDC establishment.
 
	- SES supports relative and absolute addressing.
 
	- PDS supports various error packets generation and reception.
 
	- Supports SES-PDS logical interface
 
	- Ethernet supports 100G, 200G, 400G, 800G and 1.6T as per IEEE Std 802.3.
 
	- Supports Standard IP layer
 
	- Supports Standard DLL layer
 
	- Supports Standard ethernet PHY layer with 100G PHY lanes
 
	- Callback support in all Layers to provide user control.
 
	- Rich set of configurations and parameters.
 
	- Supports Dynamic as well as Static Error Injection scenarios.
 
	- On the fly protocol checking static and dynamic assertion.
 
	- Built in Coverage analysis.
 
	- Graphical analyzer to show transactions for easy debugging
 
Deliverables
	- Deliverables Ultra Ethernet BFM’s for
	
		- PDS layer with Congestion Management
 
		- SES layer
 
		- IP layer
 
		- DLL Layer
 
		- Reconciliation layer
 
		- PCS layer
 
		- PMA layer
 
		- FEC layers (RS-FEC, BASE-R FEC)
 
		-  PMD layer
 
	
	 
	- Ethernet 100G/200G/400G/800G/1.6T layered monitors and scoreboard Test environment and Test Suite-
	
		- Basic and Directed Protocol Tests
 
		- Random Tests- Error Scenario Tests
 
		- Assertions & Cover Point Tests
 
		- User Test Suite
 
	
	 
	-  Integration Guide, User Manual and Release Note
 
	- GUI analyser to view simulation packet Flow